1. Field
Example embodiments relate to a semiconductor device. Other example embodiments relate to a multi-stack memory device.
2. Description of the Related Art
The integration density of a semiconductor device may be increased to a limit by reducing a line width because the line width below a critical value may not be realized due to the limitation of an exposure process. Also, when the line width of a storage node where data is stored is reduced below a critical value, the data retention characteristics of the storage node may be deteriorated. For example, in a storage node formed of a magnetic material having relatively small magnetic anisotropic energy, if the size of a minimum region where data is stored, for example, a bit size is reduced below a critical value, the thermal stability of the storage node may be reduced and the data retention characteristics may be deteriorated.
Therefore, a multi-stack memory device may have increased integration density by stacking storage nodes. Accordingly, the integration density may be increased without reducing the line width. This technique may be applied to various fields, e.g., a domain wall motion memory device, a resistive random access memory (RRAM) device and/or a flash memory device.
In such a multi-stack memory device, storage nodes stacked with a plurality of rows or a multi-structured wiring connected to the storage nodes may be respectively connected to a plurality of transistors formed on a substrate. In a domain wall motion memory device field, the domain wall movement of a particular storage node may be possible by the transistor. Also, in a RRAM device and the flash memory device fields, random access of data may be possible by the transistors.
However, due to structural complexity, connecting the storage nodes or the wirings to the transistors and maintaining a pitch of the storage nodes or the wirings of about 2F (F=minimum width) may be difficult. When the storage nodes or the wirings are connected to the transistors using a conventional method, a conductive plug may be disposed between every storage node or wiring, the pitch of the storage nodes or the wirings may increase to about 4F. Therefore, in the conventional multi-stack memory device, increasing the recording density per unit area as long as the pitch of the storage nodes or the wirings, and not reduced below about 4F, may be difficult.